1. Field of the Invention
Generally, the present disclosure relates to the fabrication of sophisticated integrated circuits including advanced transistor elements that comprise gate structures of increased capacitance including a high-k gate dielectric and a metal-containing cap layer.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. In a wide variety of integrated circuits, field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced for forming field effect transistors, wherein, for many types of complex circuitry, MOS technology is one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, the distance between the source and drain regions, which is also referred to as channel length. Hence, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, as the speed of creating the channel, which depends on the conductivity of the gate electrode, and the channel resistivity substantially determine the transistor characteristics, the scaling of the channel length, and associated therewith the reduction of channel resistivity, which in turn causes an increase of gate resistivity due to the reduced dimensions, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
Presently, the vast majority of integrated circuits are based on silicon due to its substantially unlimited availability, the well-understood characteristics of silicon and related materials and processes and the experience gathered during the last 50 years. Therefore, silicon will likely remain the material of choice for future circuit generations to be fabricated by using volume production techniques. One reason for the dominant role of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows the performance of subsequent high temperature processes, as are required, for example, during anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide is preferably used as a base material of a gate insulation layer that separates the gate electrode, frequently comprised of polysilicon, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has been continuously decreased to improve switching speed and drive current capability. Since transistor performance is controlled by the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a pronounced dependence of the threshold voltage on the channel length. Aggressively scaled transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current, since the thickness of the silicon dioxide layer has to be correspondingly decreased to provide the required capacitance between the gate and the channel region. For example, a channel length of approximately 80 nm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. The relatively high leakage current caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide-based gate insulation layer may reach values for an oxide thickness in the range of 1-2 nm that may not be compatible with requirements for many types of circuits, even if only transistors in speed critical paths are formed on the basis of an extremely thin gate oxide.
Therefore, replacing silicon dioxide as the material for gate insulation layers has been considered, particularly for extremely thin silicon dioxide gate layers. Possible alternative materials include materials that exhibit a significantly higher permittivity so that a physically greater thickness of a correspondingly formed gate insulation layer provides a capacitive coupling that would be obtained by an extremely thin silicon dioxide layer. It has thus been suggested to replace silicon dioxide with high permittivity materials such as tantalum oxide (Ta2O5), with a k of approximately 25, strontium titanium oxide (SrTiO3), having a k of approximately 150, hafnium oxide (HfO2), HfSiO, zirconium oxide (ZrO2) and the like.
Additionally, transistor performance may be enhanced by providing an appropriate conductive material for the gate electrode so as to replace the usually used polysilicon material, since polysilicon may suffer from charge carrier depletion at the vicinity of the interface to the gate dielectric, thereby reducing the effective capacitance between the channel region and the gate electrode. Thus, a gate stack has been suggested in which a high-k dielectric material provides an increased capacitance based on the same thickness as a silicon dioxide layer, while, additionally, leakage currents are kept at an acceptable level. On the other hand, the non-polysilicon material, such as titanium nitride and the like, may be formed so as to connect to the high-k dielectric material, thereby substantially avoiding the presence of a depletion zone.
After forming sophisticated gate structures including a high-k dielectric and a metal-based gate material, however, high temperature treatments may be required, which may result in a shift of the work function and a reduction of the permittivity of the gate dielectric, which may also be associated with an increase of layer thickness, thereby offsetting many of the advantages of the high-k dielectric in combination with the metal-containing electrode material. It is believed that the deterioration of the high-k metal gate is substantially caused by the incorporation of oxygen and a respective oxygen diffusion within the high-k dielectric material, wherein the oxygen diffusion may be fed by oxygen contained in the ambient that may come into contact with the high-k dielectric during the processing of the devices. Since, for instance, hafnium- and zirconium-based oxides grow very fast due to the high affinity to oxygen and its diffusion even at moderate temperatures, a significant modification of the characteristics of the high-k dielectric material may be observed, for instance an increased layer thickness and thus a reduced dielectric constant, which may be even further pronounced at moderately high temperatures of approximately 950-1300° C., as may typically be used during activation treatments and the like.
In addition to a significant modification of the high-k dielectric material, also the work function of the metal-containing electrode in the gate stack may be shifted towards the center of the band gap, thereby modifying the threshold voltage of respective transistors. Due to the high oxygen affinity of the high-k dielectric material and due to the exposure to wet chemical etch procedures and cleaning processes, usually the gate stack is encapsulated after the patterning process in order to enhance stability of the high-k dielectric material and the respective metals in the gate stack. For this purpose, silicon nitride has proven to be a promising material due to its oxygen blocking characteristics. Hence, in typical conventional process flows, a silicon nitride liner with a thickness in the range of approximately 1-5 nm may be formed on exposed surface areas of the patterned high-k gate stack, wherein appropriate deposition techniques are used so as to not unduly affect device characteristics and/or the subsequent manufacturing steps. For example, well-established low pressure chemical vapor deposition (LPCVD) techniques and/or multi-layer deposition techniques may be applied for forming the silicon nitride liner.
In addition to providing sophisticated gate electrode structures by using high-k dielectric materials and metal-containing gate electrode materials, other approaches have been developed in order to enhance transistor performance for a given gate length and a thickness of a gate dielectric material. For example, by creating a certain strain component in the channel region of the transistor elements, the charge carrier mobility, and thus the overall conductivity of the channel, may be enhanced.
Many of these strain-inducing mechanisms are based on a strained or stress-inducing material that is formed in close proximity to the channel region of the transistor under consideration. For example, frequently, a strain-inducing semiconductor material is embedded into the drain and source areas, while, in other cases, in addition or alternatively to this mechanism, a highly stressed dielectric material is formed above the gate electrode structure and the transistor, thereby also efficiently transferring strain into the channel region. Generally, upon further scaling the transistor dimensions, the strain transfer efficiency may significantly depend on the lateral distance of any strain-inducing materials, which in turn may require a corresponding scaling of the lateral offset, thereby also requiring a reduction of the thickness of any spacer structures and the like, which may also include the protective liner material formed on sidewalls of the complex gate electrode structures. Also with respect to other aspects, such as complex lateral dopant profiles of the drain and source regions, a reduced thickness of the protective liner material may be highly desirable. Consequently, the liner material intended for enhancing integrity of the sensitive gate electrode structure during the further processing for completing the transistor configuration may be reduced in thickness, which, however, may result in severe yield losses due to material loss in the gate electrode structure. Without intending to restrict the present application to any theory, it is nevertheless believed that patterning irregularities, in particular at the foot of the complex gate electrode structure, may result in inferior coverage of this area when selecting an appropriate thickness for the liner material. That is, upon patterning the complex gate layer stack, which may, in conventional approaches, result in a certain tapered cross-sectional shape of the gate electrode structure at the foot thereof, for instance in view of enabling superior process control on the basis of electron microscopy for adjusting the electrically effective gate length, a reduced degree of coverage by the liner material may thus increase the probability of an interaction with aggressive chemical agents during the further processing of the semiconductor device. For example, an SPM (sulfuric acid hydrogen peroxide mixture) is a very efficient cleaning agent in order to remove any contaminants, metal residues and the like after performing the complex patterning process and prior to performing any further critical processes. Omitting a cleaning step in this manufacturing stage or providing a less efficient cleaning recipe may significantly increase overall defectivity, which may thus result in a significant yield loss at this manufacturing stage. On the other hand, the reduced degree of coverage at the foot of the gate electrode structures may contribute to an increased probability of removing significant amounts of the metal-containing electrode material, such as the titanium nitride, which may thus result in a significant variability of the resulting transistor characteristics, since, for instance, the electrically effective gate length may be influenced by a loss of titanium nitride material, thereby causing variations of the threshold voltage and the like. For example, pronounced transistor variability has been observed across individual dies and also across substrates, thereby contributing to increased yield loss or to an increased amount of semiconductor devices of reduced performance.
Therefore, it has been proposed to form a defined undercut below the polysilicon material, that is, to remove a portion of the sensitive titanium nitride, high-k and any base oxide material in order to achieve a superior encapsulation, in particular of the undercut area, when forming the silicon nitride liner material. To this end, in some conventional approaches, a diluted SPM agent is applied prior to actually forming the liner material, thereby creating a desired undercut area. It turns out, however, that the degree of under etching upon applying the diluted SPM solution critically depends on the process conditions, in particular on the concentration of the solution, which may result in a substantially non-controllable lateral etch rate so that also significant transistor variability may be observed, although the subsequent encapsulation of the gate electrode structure may provide superior coverage at the undercut area. In other conventional approaches, a reactive ion etch process which is applied in order to pattern the complex gate layer stack may typically have a certain lateral etch rate and may also be used upon appropriately selecting the etch chemistry in a final phase of the etch sequence so as to form an undercut area. Generally, the reduced lateral etch rate compared to the wet chemical process performed on the basis of diluted SPM may generally provide superior controllability, wherein, however, even any subtle modifications of the gate layer stack may also result in significantly different etch results upon forming the undercut area. Moreover, generally, the polysilicon profile may also be affected, thereby resulting in a degraded overall gate profile.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.